Patent · US Expired

IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout

US6973634B1 · kind B1 · utility

11Cited by

112References

18Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Steven Teig · Menlo Park, US
Andrew Caldwell · Santa Clara, US
Etienne Jacques · Sunnyvale, US

Key dates

Filing date	Aug 26, 2002
Grant date	Dec 6, 2005
Priority date	—
Expiry date	Feb 6, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Some embodiments of the invention provide a region of an integrated-circuit (“IC”) layout that has a plurality of interconnect layers, where at least one particular layer has more than one preferred interconnect direction. In some of these embodiments, the region has several interconnect layers that have more than one preferred wiring direction each.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.