Healing of micro-cracks in an on-chip dielectric
US6975017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2004 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Jul 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment there is provided a method comprising performing a sawing operation on a wafer; and treating the wafer to at least reduce a propagation of micro-cracks formed in the wafer during the sawing. In another embodiment there is provided a semi-conductor die comprising a substrate having a central first portion, and a peripheral second portion around the central first portion; an integrated circuit formed on the central first portion; and a guard ring disposed between the first and second portions of the substrate to prevent a propagation of cracks found in that second portion to the first portion, wherein the second portion includes micro-cracks filled with a crack-healing material to arrest propagation of the micro-cracks beyond the guard ring and into the central first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.