Semiconductor chip package and method of manufacturing same
US6975025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Dec 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package, an electronic system, and a method of manufacturing such package. A lower structure includes a lower insulating layer and a metal layer made of separate electrical conductors. A wall defines a cavity on the metal layer. Electrical conductors extend from the metal layer to contact points elsewhere in the semiconductor chip package. Conductor members are positioned on the electrical conductors of the metal layer. A semiconductor chip is positioned on the conductor members within the cavity, with an isolation area between the semiconductor chip and the wall. The electrical contacts on the semiconductor chip contact the conductor members to couple the semiconductor chip to the contact points. Underfill material is provided within the isolation area between the perimeter surface and the wall, and is prevented by the wall from spreading to other areas. Placement of the semiconductor chip within the cavity reduces the package thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.