Factorized power architecture with point of load sine amplitude converters
US6975098B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2003 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Jul 31, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A Factorized Power Architecture (“FPA”) method and apparatus for supplying power to highly transient loads such as microprocessors includes a front end power regulator (“PRM) which provides a controlled DC bus voltage which is converted to the desired load voltage using a DC voltage transformation module (“VTM”) at the point of load. The VTM converts the DC bus voltage to the DC voltage required by the load using a fixed transformation ratio K=Vout/Vin where Vin>Vout and with a low output resistance. The response time of the VTM, TVTM is less than the response time of the PRM, TPRM. A first capacitance, C1, across the load is made large enough to support the microprocessor current requirement within a time scale, T1, which is preferably greater than or equal to the characteristic open-loop response time of the VTM by itself, TVTM. A second capacitance, C2, at the input of the VTM is made large enough to support the microprocessor current requirement within a time scale, T2, which is preferably greater than or equal to the closed-loop response time of the front end power regulator, TPRM. Feedback may be provided from a feedback controller at the point of load to the front end or to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.