Timing loop and method filter for a digital communications system
US6975676B1 · kind B1 · utility
7Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2000 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Apr 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A timing loop is used in a data communications receiver to time lock the receiver to a transmitter sending data across a communications loop, where the receiver includes a linear equalizer for correcting signal distortion associated with the communications loop. The timing loop includes a timing equalizer filter functionally positioned to provide an equalized signal to the phase detector portion of the timing loop. After the linear equalizer trains, the equalizer coefficients are copied to the timing equalizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.