Property specific testbench generation framework for circuit design validation by guided simulation
US6975976B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2000 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Dec 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of this work is to generate property-specific testbenches that are targeted either at proving the correctness of a property or at finding a bug. It is based on performing property-specific analysis on iteratively less abstract models of the design in order to obtain interesting paths in the form of a Witness Graph, which is then targeted during simulation of the entire design. This testbench generation framework will form an integral part of a comprehensive verification system currently being developed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.