AC LSSD/LBIST test coverage enhancement
US6976199B2 · kind B2 · utility
5Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2002 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Apr 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318577
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In an LSSD/LBIST scan design, AC scan test coverage is enhanced with a scan chain configuration capable of selectively inverting scan-in signals. For example, one or more XOR gates are inserted in the scan chain. The XOR gates is controlled by a control signal preferably coming from a primary input such that original scan-in signals as well as inverted scan-in signals are shifted into the scan chain. The proposed configuration significantly enhances the AC test coverage for a scan chain having adjacent SRLs feeding the same cone of logic by adding a simple logic circuit such as an XOR gate between the adjacent SRLs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.