Inter-method control transfer for execution engines with memory constraints
US6976254B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2001 |
| Grant date | Dec 13, 2005 |
| Priority date | — |
| Expiry date | Apr 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/449
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bytecode execution system and method for increasing the execution speed of invoking and returning from Methods while minimizing the memory footprint required to support this. The system includes a virtual machine with a class loader and an interpreter or, alternatively, a hardware accelerator. Speed and memory enhancements are realized by establishing an activation stack frame template with a set of criteria. Each Method from subject code is examined to determine whether the Method conforms to the criteria of the stack frame template. If the Method conforms, an activation frame for that Method based on the activation stack frame template is created when the Method is invoked. Otherwise, an activation frame based on standard virtual machine criteria is created. An access structure is associated with each Method and a Method routing structure is created for each class.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.