Semiconductor chip stack structure
US6977439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Dec 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.