32V H-bridge driver with CMOS circuits
US6977533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2004 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6871
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A motor bridge driver interlace, implemented in an ASIC using cost-efficient CMOS technology, is designed to control four external MOS power transistors in a H-bridge configuration for DC-motor driving to achieve accurate and fast switching. Main components of the interface are a charge pump for generating the control voltage for the high-side N-channel MOS transistors, high-side (HSD) circuits, low-side (LSD) circuits and a complex digital interlace for supplying the control signals in a programmable timing scheme. A “strong” charge pump is used to realize a simple CMOS switch to steer the output to the high-side transistors of said H-bridge. The motor bridge is connected to the battery supply by an additional N-channel MOS transistor to implement a reverse supply protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.