Rational frequency synthesizers
US6977556B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2000 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | May 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single loop PLL frequency synthesizer for operation in the MHz to GHz range, suitable for integration in integrated circuits, operates at high comparison frequencies thus achieving superior phase noise performance, having wide loop bandwidths while able to tune in small frequency steps. It is based on the fact that the output frequency and the reference clock frequency always have a rational relationship, and so can always be represented as a ratio of two integer numbers. This ratio is expanded into various expressions of equivalent fraction expansions taking the form of a series of divided, added or subtracted terms, each being a rational number in itself. This ratio is realized in hardware through stages of frequency conversions using single sideband mixers (either the upper or lower sideband, and frequency dividers. This process of frequency translation thus generates the comparison frequency to which the PLL phase-locks the VCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.