Addressing a cache
US6977657B2 · kind B2 · utility
2Cited by
11References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Aug 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.