Apparatus for adjusting phase of clock signal based on phase error calculated from sampled values of readout signal
US6977879B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2000 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Nov 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clock adjustment apparatus for adjusting a phase of a clock signal based on a phase error thereof is provided in a data reproduction system which samples a readout signal from a recording medium in synchronism with the clock signal, and reproduces data in accordance with a Viterbi algorithm by using sampled values of the readout signal. The recording medium is recorded with the data modulated in accordance with a recording rule of a predetermined partial response characteristic. The clock adjustment apparatus includes a phase error calculation circuit which calculates the phase error of the clock signal based on the sampled values of the readout signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.