Shared buffer type variable length packet switch
US6977941B2 · kind B2 · utility
18Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2001 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Aug 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.