Synchronization of interrupts with data packets
US6978331B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2000 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Jul 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0092
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for conveying data over a packet-switching network (26). Data are received from a peripheral device (25) for transmission via the network to a memory (22) associated with a central processing unit (CPU) (21), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface (32) serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.