Error-correcting content addressable memory
US6978343B1 · kind B1 · utility
139Cited by
15References
43Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2002 |
| Grant date | Dec 20, 2005 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to contents of respective rows of the CAM cells, and the column parity storage elements store column parity values that correspond to respective columns of the CAM cells. A bit error in the array is detected through row and column parity checking that uniquely identifies the row and column location of the error and enables correction of the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.