Semiconductor devices and manufacturing methods
US6979612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2004 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Jan 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
A semiconductor device in certain embodiments includes an insulating layer provided above the upper surface of a semiconductor substrate, and a capacitive element section and a resistance element section formed above the insulating layer. In the capacitive element section, a gate electrode serving as an opposite electrode for the capacitive element is formed above the insulating layer. The gate electrode is covered with a dielectric layer comprising silicon oxide, silicon nitride or tantalum oxide, and an electrode for the capacitive element comprising MoSix is provided above the dielectric layer. The resistance element section has a resistance element comprising MoSix formed simultaneously with the electrode for the capacitive element in the same process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.