Interlayer connections for layered electronic devices
US6979643B2 · kind B2 · utility
2Cited by
10References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Nov 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for forming interlayer connections, metal conducting paths in an overlaying layer and vias forming the deposit in one and the same operation. In an interlayer connection formed in this manner the vias are provided integral with connecting conducting paths in the overlaying layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.