Intermediate substrate
US6979890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2005 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | May 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An intermediate substrate is provided which reduces the effect of the difference in the coefficients of linear expansion between the terminals of the substrate and those of a semiconductor integrated circuit device, and which thus lowers the likelihood of disconnection due to thermal stress. The intermediate substrate, which is a planar member made of a polymeric material, includes a substrate core including a main core body having formed therein a sub-core compartment, and a ceramic sub-core section accommodated in the compartment. A first terminal array on the first principal surface side includes two types of terminals, functioning either as power source terminals or ground terminals, and a signal terminal. The array occupies an area entirely included within an orthogonally projected region of the sub-core section projected onto a reference plane parallel to the planar surface of the substrate core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.