Synchronous first-in/first-out block memory for a field programmable gate array
US6980027B2 · kind B2 · utility
7Cited by
7References
1Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 22, 2004 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.