Power on reset techniques for an integrated circuit chip
US6980037B1 · kind B1 · utility
5Cited by
27References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1998 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Aug 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L3/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.