Memory cell architecture for reduced routing congestion
US6980462B1 · kind B1 · utility
41Cited by
1References
36Claims
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Key dates
| Filing date | Nov 18, 2003 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Apr 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory cell architecture is provided herein for reducing, or altogether eliminating, chip-level routing congestion in System-on-Chip environments. Though only a few embodiments are provided herein, features common to the described embodiments include: the formation of bitlines in a lower-level metallization layer of the memory array, and the use of word lines and ground supply lines, both formed in inter-level metallization layer(s) of the memory array, for effective shielding of the bitlines against routing signals in the chip-level routing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.