Method and system for fast ethernet serial port multiplexing to reduce I/O pin count
US6980563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2001 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Oct 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.