Critical datapath error handling in a multiprocessor architecture
US6981079B2 · kind B2 · utility
27Cited by
21References
19Claims
0Family size
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Key dates
| Filing date | Mar 21, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Feb 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A interrupt is generated for all processors in a multiprocessor system when a critical datapath experiences an error. Serialization code in the interrupt handling routine for that interrupt suspends all processors except one and places the suspended processors in a waiting queue while the one processor handles the error. After the error has been handled, the remaining processors are allow to execute the interrupt handler, which simply exits detecting no error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.