Programmable controller with sub-phase clocking scheme
US6981167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Nov 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/15063
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A parallel processor with a built-in sub-phase clocking scheme is provided to execute sequentially executed programmable logic controller (PLC) programs in a parallel method. A translator program will translate the PLC logic design from a coding language into Electronic Design Interchange Format and that will be eventually converted to a hardware or software embodiment of the logic. The processor provides a plurality of sub-phase clock periods. The translator assigns to the same sub-phase period program elements that process their tasks in the same range of time. The elements are grouped into sub-phase so that logic elements are performed lock-step to ensure that downstream element are performed at a time when they have valid values at their inputs. The processor consequently avoids race conditions in the system and allows the parallel execution speedup of programs written for a sequential machine such as a PLC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.