Redundant memory sequence and fault isolation
US6981173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Mar 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion across on a plurality of memory cartridges each containing a plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). Each memory cartridge includes an independent memory controller and a corresponding control mechanism in the host/data controller to interpret the independent transitioning of each memory cartridge between various states, including a redundant-ready and a powerdown state to facilitate “hot-plug” capabilities utilizing the removable memory cartridges. Fault information may be passed between the individual memory controllers and the host/data controller to facilitate expedient fault isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.