Separation of debug windows by IDS bit
US6981178B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Jul 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon detection of an interrupt. The interrupt during debug bit has a first digital state if the central processing unit is in a debug halt state and a second digital state if the central processing unit is not in a debug halt state. Upon return from an interrupt the central processing unit enter a debug halt state if the interrupt during debug bit has the first state. The return address and the interrupt during debug bit can be embodied in a push-pop stack. The interrupt during debug bit register can be an unused least significant bit of the return address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.