Interconnect system with error correction
US6981200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2001 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Aug 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0072
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for transmission of digital data in a form of data packets through links carrying data packets with error correction, includes the steps of enveloping a sent packet data, first with an error detection scheme, and secondly with an error correction scheme. The error correction applies to both the sent packet data and to the error detection field. If an error in either of these fields occurs, the error correction scheme attempts to correct it. Error correction may fail in which case the packet is dropped. If error correction does not fail, there is still a possibility that there was an error which error correction did not correct correctly, or did not detect at all because the power of the correction scheme was exceeded. In these cases, the error detection scheme provides a method or means to detect such errors and drop the packet. Corresponding interconnect system with error correction, encode and decode for such are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.