Process for decoding signals and system and computer program product therefore
US6981201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | Oct 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/41
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for decoding digital signals subjected to block coding includes a post-processor that corrects the codewords affected by error, identifying them with the most likely sequence that is a channel sequence and that satisfies a syndrome check. The post-processor is a finite-state machine described by a graph that represents the set of error events. The post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths that accumulate an invalid number of error events or an excessive number of wrong bits, paths that accumulate a total reliability higher than a given threshold, paths with an invalid check on the received sequence, and paths that reveal an invalid syndrome after having reached a maximum number of events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.