Method of ITO layout to make IC bear the high-volt electrostatic discharge
US6981234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | May 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of ITO layout to make IC bear the high-volt electro static discharge, wherein the major steps include: designing the suitable circuit impedance and Layout at the position of Driver IC bonding and Interface on LCD Module(COG type) in accordance with the function and use of each pin; improving the protection function of ESD(Electro Static Discharge) in increasing the LCD Module assembly on the product of the client; wherein: connecting the pins of all VDD or VSS together at the bottom of the IC and the width of ITO layout spreading over the bottom of IC without influencing the layout of other pins after connecting VSS or VDD. Discharge the static electricity that enters the position of Module Interface and dissipate the electro static discharge by means of the ITO layout design of the big area to improve the protection ability of IC for the electro static discharge. Serial connect an extremely high impedance(3K˜50K Ω) in the Reset Pin. Increase the value (100˜1000 Ω) of ITO circuit impedance of Date bus, such as CS1.D/C,WR,RD,D0˜D7,C86 etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.