Metal-metal capacitor array
US6982454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Nov 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/711
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitor includes a semiconductor substrate, a bottom conductive pattern, first to third insulating layers, first to third metal plates and a connecting pattern. The bottom conductive pattern is formed on the semiconductor substrate. The first to third insulating layers are formed on the bottom conductive pattern, the first and second metal plates, respectively. The first metal plate is formed on the first insulating layer within a first area. The first metal plate is electrically connected to the bottom conductive pattern. The second metal plate is formed on the second insulating layer within the first area. The second metal plate has an opening in the center thereof. The third metal plate is formed on the third insulating layer. The connecting pattern is formed through the second and third insulating layers and the opening of the second metal plate. The connecting pattern electrically connects the first and the third metal plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.