Programmable digital filter implementation for loss-of-signal detection for serial communications applications
US6983299B1 · kind B1 · utility
0Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Aug 28, 2001 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Apr 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals each representative of the state of the input signal during a plurality of clock cycles. The second circuit may be configured to present a filtered signal in response to a selected number of the intermediate signals having a predetermined state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.