Apparatus for reducing the overhead of cache coherency processing on each primary controller and increasing the overall throughput of the system
US6983396B2 · kind B2 · utility
34Cited by
14References
16Claims
0Family size
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Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Jun 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bridged controller for reducing the overhead of cache coherency processing on each of a plurality of primary controllers and increasing the overall throughput of the system. The bridged controller interfaces with dual-active pair of host-side controllers and the backend disk drive buses. The third controller allows a doubling of the number of backend busses, reduces the overhead of cache coherency processing on each primary host-side controller and doubles the overall throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.