Detecting bit errors in a communications system
US6983403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2001 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Oct 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/203
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Error codes output from a serializer/deserializer in a node of a communications network are detected by error decode logic that assumes that each new error occurrence reflects a one bit error in the word giving rise to the error code. Each error occurrence is then counted. When the error count reaches a predetermined limit (e.g., 250 errors), the total bit count required to accumulate the 250 errors is then determined. The total bits can be determined based on a clock count (time). The BER is then calculated based upon the fixed error limit and the total bit count. This BER is then reported and used to determine the health of the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.