Method of reducing the number of configuration bits by eliminating the unused configuration bits
US6985011B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2003 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Feb 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second configuration frame is related to the first configuration frame. The method further includes creating a third configuration frame by placing information from the second configuration frame into positions indicated by the first configuration frame. The method further includes configuring the PLD using the third configuration frame. In this manner, the second configuration frame may occupy less space in the memory, and may be read more quickly, than a frame that also included position information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.