Amplifier arrangement, circuit and method with improved common mode rejection ratio
US6985037B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2003 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/261
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A load driver circuit is provided with an improved common mode rejection ratio. A voltage regulator (150) regulates a ground voltage (120) in response to variations in input voltage (110) and provides a regulated ground voltage. An amplifier stage has a first amplifier (140) with sense inputs coupled to receive voltage signals from a sense resistor (130) of the load driver circuit. The first amplifier (140) is powered by the input voltage (110) and the regulated ground voltage respectively, such that the common mode rejection ratio of the load driver circuit is reduced. In this way an arrangement, circuit and method is provided in which CMRR is drastically improved, rendering a single (or first) stage of a current sensing load driver circuit substantially immune to common mode noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.