Clock generating circuit and method
US6985041B2 · kind B2 · utility
9Cited by
20References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2002 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.