System and method of testing a transceiver
US6985823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2003 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/20
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system and method for testing the jitter tolerance and signal attenuation tolerance of an optoelectronic device is disclosed. The system includes a generation circuit, delay circuit and comparison circuitry. A first sequence of bits is generated, delayed, and sent to the optoelectronic device. The optoelectronic device receives the bits and retransmits them as a second sequence to the comparison circuitry, which compares the two bit sequences to determine a bit error rate. The bit error rate is then used to determine the jitter tolerance and, in an alternate embodiment, the signal attenuation tolerance of the optoelectronic device being tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.