Variable cycle interrupt disabling
US6985986B2 · kind B2 · utility
4Cited by
210References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Oct 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.