FIFO memory with programmable data port widths
US6986004B1 · kind B1 · utility
5Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2003 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Jan 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory provides a programmable write port data width and an independently programmable read port data width. The independence between the programmable write port data width and the programmable read port data width is achieved without the use of a third clock domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.