Conditional execution of coprocessor instruction based on main processor arithmetic flags

US6986023B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Nigel C. Paver · Austin, US
• William T. Maghielse · Austin, US
• Wing K. Yu · Austin, US
• Jianwei Liu · Fremont, US
• Anthony Jebson · Huntingdon, GB
• Kailesh B. Bavaria · Austin, US
• Rupal Parikh · Hillsboro, US
• Deli Deng · Austin, US
• Mukesh Patel · Round Rock, US
• Mark Fullerton · Austin, US
• Murli Ganeshan · Austin, US
• Stephen Strazdus · Chandler, US

Key dates

• Filing date: Aug 9, 2002
• Grant date: Jan 10, 2006
• Expiry date: Dec 2, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3885
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.