Register capable of corresponding to wide frequency band and signal generating method using the same
US6986072B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Jan 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.