Method and apparatus for testing a high speed data receiver for jitter tolerance
US6986091B2 · kind B2 · utility
3Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.