Erasure-and-single-error correction decoder for linear block codes
US6986092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2001 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Nov 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/37
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for efficiently performing erasure-and-single-error correction block decoding on a received block of symbols previously coded column-wise with an (N, K) linear block code and row-wise with an error detection code (e.g., a CRC code). Initially, each row of the received block is marked as either an erased row or an un-erased row. To perform erasure-and-single-error correction block decoding on the received block, a codeword corresponding to a column of the received block containing an undetected symbol error is initially identified. The location of the symbol error in the codeword is then determined based on a particular block decoding scheme and corresponding to the selected (N, K) block code. The row of the received block containing the symbol error is then marked as an erased row. Block decoding may then be performed for the received block with the newly marked erased row containing the symbol error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.