Method of reducing miscorrections in a post-processor using column parity checks
US6986098B2 · kind B2 · utility
170Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Jun 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0065
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and system for reducing miscorrections of data in a post-processor. In an embodiment of the invention, the system and method may compare a result of an exact match function and a metric for each row of a reconstructed data block to determine if a correction should be made. An algorithm for performing an exact match function may include a column parity check syndrome, a matched filter error syndrome, and an error mask of the present invention. If a result of an exact match function is an exact match, a priority of correction may be given to the row in which the exact match was produced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.