Practical method for hierarchical-preserving layout optimization of integrated circuit layout
US6986109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2003 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Jan 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.