Method for estimating substrate noise in mixed signal integrated circuits
US6986113B2 · kind B2 · utility
14Cited by
5References
4Claims
0Family size
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Key dates
| Filing date | Nov 10, 2003 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Dec 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise generated by a digital circuit and input/output circuitry to be implemented in the integrated circuit are estimated. A substrate netlist is generated for the integrated circuit. A floorplan is determined for the integrated circuit. Transient simulations are run with predetermined input values. Finally, it is determined if predetermined noise requirements are met in results of the transient simulations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.