Methods and apparatus for improving high frequency input/output performance
US6987326B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2005 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Jan 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An impedance matching circuit is provided for an IC arranged on a package that matches an impedance of an external load. The circuit includes a package, an IC that is arranged on the package, and an impedance matching circuit. The impedance matching circuit includes a first bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with said IC, a capacitance element arranged on the IC, and a second bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with one end of said capacitance element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.