Pipelined analog-to-digital converter (ADC) with 3-bit ADC and endpoint correction
US6987477B1 · kind B1 · utility
10Cited by
3References
15Claims
0Family size
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Key dates
| Filing date | Oct 4, 2004 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Oct 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipelined analog-to-digital converter (ADC) in which one less pipeline stage is needed while the output ADC stage has its resolution increased by one bit, thereby advantageously providing for decreased circuit area, lower power consumption and endpoint correction, with minimal additional circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.