High speed network processor
US6987760B2 · kind B2 · utility
16Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2001 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Dec 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5685
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.